A. Field of the Invention
The present invention relates to vertical insulated gate semiconductor devices for high power use. Specifically, the present invention relates to super-junction trench-gate semiconductor devices which include trenches, trench gates in the respective trenches, each of the trench gates including an insulator film formed in the trench and a control electrode formed in the trench with the insulator film interposed between the control electrode and trench, and a super-junction layer such as an alternating conductivity type layer in the semiconductor substrate thereof.
B. Description of the Related Art
Recently, intensive efforts have been focused on improving the performance of power semiconductor devices, in order to meet the demands in the field of power electronics for power supply apparatuses with reduced dimensions and higher capabilities. The improved performance sought for the power semiconductor devices include realizing a higher breakdown voltage in the power semiconductor devices, realizing a higher current capacity therein, reducing the losses caused therein, realizing a higher breakdown withstanding capability therein, and making the power semiconductor devices work at a higher speed. A super-junction substrate is known as a substrate structure favorable for introducing the improvements described above. A power semiconductor device having a planar MOS structure or a trench MOS structure has been proposed as a surface structure of a power semiconductor device favorable for introducing the improvements described above.
The super-junction semiconductor substrate is a semiconductor substrate including an alternating conductivity type layer including semiconductor regions of a first conductivity type (e.g., n-type drift regions) and semiconductor regions of a second conductivity type (e.g., p-type partition regions) bonded alternately to each other.
A technique that facilitates realizing a low on-resistance by the super-junction trench-gate MOSFET structure that combines the super-junction semiconductor substrate described above with a vertical MOS power device structure and a trench MOS power device structure also known to those skilled in the art. For example, a conventional semiconductor device that employs a super-junction semiconductor substrate is disclosed in FIG. 16, in which the pn-junctions in alternating conductivity type layer 1601 and trench gates 1602 are extended perpendicularly (cf. Published Unexamined Japanese Patent Applications 2000-260984 and 2005-19528). Other conventional semiconductor devices that employ super-junction semiconductor substrates as shown in FIGS. 17 through 19B have been disclosed, in which the pn-junctions in alternating conductivity type layers 1701, 1801 and 1901 and respective trench gates 1702, 1802 and 1902 are extended in parallel to each other (cf. Published Unexamined Japanese Patent Applications 2002-76339 and 2001-332726). The MOSFETs that include the super-junction trench gates as described above realize low on-resistance.
However, it has been well known to those skilled in the art that there exists a tradeoff relation between the on-resistance per unit area and the avalanche breakdown voltage (that has a certain relation with the breakdown voltage of the device) in MOSFETs and such unipolar devices. The tradeoff relation exists in the devices described in the Published Unexamined Japanese Patent Applications 2000-260984, 2005-19528, 2002-76339, and 2001-332726. If one tries to decrease the on-resistance, the breakdown voltage will be decreased. If one tries to increase the breakdown voltage, the on-resistance will be increased.
For example, although the on-resistance may be decreased by the semiconductor device structure described in Published Unexamined Japanese Patent Application 2001-332726, the breakdown voltage is decreased. This is because the trench bottom cuts across the region of the semiconductor substrate in which the electric field strength is high. Moreover, it has been known that there exist limits in silicon and SiC, beyond which both the on-resistance and the breakdown voltage can not exceed physically. Hereinafter, the limits will be referred to as the “semiconductor limits.”
In designing MOSFETs and such semiconductor devices, the semiconductor limits are considered as the characteristics of the substrate section in the MOSFETs and such semiconductor devices. However, the influences of the voltage drop and the breakdown voltage lowering caused in the MOS channel section by making the semiconductor device work as a MOSFET are not considered. Therefore, the performance of the semiconductor device as a MOSFET are impaired.
Since the channel is longer in the structure shown in FIGS. 19A and 19B than in the structure shown in FIGS. 18A and 18B, the voltage drop is larger in the structure shown in FIGS. 19A and 19B than in the structure shown in FIGS. 18A and 18B.
Since the semiconductor devices are designed considering the variations that will be caused through the manufacture thereof, the semiconductor devices are not always provided with respective structures that facilitate exhibiting the best performances.
In view of the foregoing, it would be desirable to obviate the problems of the conventional techniques described above. It would also be desirable to provide a semiconductor device that facilitates preventing the on-resistance thereof from increasing, obtaining a higher breakdown voltage, and reducing the variations caused in the characteristics thereof. It would be further desirable to provide a method of manufacturing such a favorable semiconductor device as described above.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.